This invention relates generally to a DC amplifier, and more particularly to an offset balancing method and apparatus for such amplifier.
DC amplifiers include a single or a plurality of amplifier stages each coupled by way of DC coupling components and find wide application in wideband amplifiers for electronic instrumentation products, such as vertical amplifiers for oscilloscopes. For oscilloscope applications, amplifiers are required to exhibit flat frequency response, and low drift, and normally take differential circuit configuration including gain control and polarity switching sections.
A typical DC amplifier suited for such applications is shown in FIG. 1. The DC amplifier comprises input terminal 10, paraphase input amplifier stage 12, gain and polarity control intermediate state 16, and output amplifier stage 18. Input stage 12 comprises a pair of transistors Q1-Q2, gain setting resistor R1 coupled between the emitters of transistors Q1-Q2, emitter long-tail resistors R2-R3 and frequency response compensation network 14 that may include both variable and fixed capacitors and resistors. Coupling resistor R1 may be switched to a plurality of different values, or transistors Q1-Q2 may be multiple-emitter transistors including respective coupling resistors of different reseitance for switching the gain of the DC amplifier. Intermediate stage 16 includes two pairs of transistors Q3-Q4 and Q5-Q6, a pair of diodes D1-D2 and bias circuitry for supplying a controllable bias current to diodes D1-D2. This state 16 provides stabilized output of any desired gain and polarity depending linearly on the difference current flowing through diodes D1 and D2. Output stage 18 comprises a pair of common base transistors Q7-Q8, the bases of which are coupled to the junction voltage of voltage divider consisting of resistors R16 and R17. The collectors of transistors Q7 and Q8 are tied to voltage source (++) each through load resistor R18 and R19, respectively, and also define a pair of output terminals 20a and 20b.
The bias circuit for diodes D1 and D2 in intermediate stage 16 comprises fixed resistors R8 through R14, variable resistor R15 and a single pole, double throw switch S2 that controls the polarity. Variable resistor R15 is used to control the gain of the DC amplifier. On the other hand, connected to the base of transistor Q2 in input amplifier stage 12 are fixed resistors R4 through R6, variable resistors R7 and R0 and switch S1 which is operably ganged with S2.
In operation, input stage 12 converts the single-ended input signal applied to input terminal 10 into a differential or push-pull output currents from the collectors of transistors Q1 and Q2. Variable resistor R7 provides a controllable base bias voltage to Q2 to offset any imbalance of the amplifier, i.e. to provide equal or balanced collector output currents from transistors A1 and Q2 when the input signal is zero. Resistor R7 is, therefore, called "variable balance". The collector current of transistor Q1 is split by transistors Q3 and Q4 before reaching the emitters of transistors Q7 and Q8, respectively. Similarly, the collector current of transistor Q2 is split by transistor Q6 and Q5. The current split ratio of transistors Q3-Q4 and Q5-Q6 is a function of the bias current to diodes D1 and D2. Since the collector signal currents from transistors Q3 and Q6 are opposite polarity to each other and so are the collector signal currents from transistors Q4 and Q5, they are subtracted at the respective node or the emitter of transistors Q7 and Q8. Variable resistor R15 is used to control the gain of the DC amplifier by controlling the current splitting ratio. Switch S2 is used to select either normal or inverted gain of the DC amplifier. In the shown position of S2, more bias current flows in diode D2, thereby rendering transistors Q4 and Q6 more conductive. The output voltage at output terminal 20a is in phase with respect to the input signal at input terminal 10 because the collector current of transistor Q6 is predominant over that of transistor Q3 at output terminal 20a. At the other (or upper) position of switch S2, more bias current flows in diode D1, thereby switching the DC amplifier to an inverting amplifier. The porper offset voltage is normally changed as the amplifier polarity is switched because of differences in circuit parameters, especially electrical characteristics of transistors Q3 through Q6. The inverted balance control resistor R0 is used for offset balancing in the inverted position of the amplifier.
Careful selection of the circuit parameters and components may minimize the need for inverted balance control, but will increase the production cost. Another problem is the need for very complicated circuitry and offset balancing procedures when the amplifier includes a gain switching stage to provide a plurality of gains of the DC amplifier. For example, when emitter coupling resistor R1 is changed, by means practical in monolithic integrated circuits, to provide a different amplifer gain, the proper offset balancing voltage may also be different, thereby making the offset balancing circuit very complicated.